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data sheet ics85314agi-11 revision f september 16, 2013 1 ?2013 integrated device technology, inc. low skew, 1-to-5 differential-to-2.5v, 3.3v lvpecl fanout buffer ics85314i-11 general description the ics85314i-11 is a low skew, high performance 1-to-5 differential-to-2.5v, 3.3v lvpecl fanout buffer. the ics85314i-11 has two selectable differential clock inputs. the clk0, nclk0 and clk1, nclk1 pairs can accept most standard differential input levels. the clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the ics85314i-11 ideal for those applications demanding well defined performance and repeatability. features five differential 2.5v/3.3v lvpecl outputs selectable differential clkx, nclkx inputs clk0, nclk0 and clk1, nclk1 pairs can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl maximum output frequency: 700mhz translates any single-ended input signal to 3.3v lvpecl levels with resistor bias on nclk input output skew: 30ps (maximum) propagation delay: 1.8ns (maximum) lvpecl mode operating voltage supply range: v cc = 2.375v to 3.8v, v ee = 0v -40c to 85c ambient operating temperature lead-free (rohs 6) packaging 12 3 4 5 6 7 8 9 10 2019 18 17 16 15 14 13 12 11 q4 nq3 q3 nq2 q2 nq1 q1 nq0 q0 nq4 v cc nclk_en v cc nclk1clk1 reserved nclk0 clk0 clk_sel v ee q1nq1 nclk_en clk0 nclk0 pulldown pulldown clk_sel pulldown pullup clk1 nclk1 pulldown pullup d ck q q0nq0 q2nq2 q3nq3 q4nq4 01 pin assignment ics85314i-11 20-lead tssop 6.5mm x 4.4mm x 0.92mm package body g package top view ics85314i-11 20-lead soic 7.5mm x 12.8mm x 2.3mm package body m package top view block diagram
ics85314agi-11 revision f september 16, 2013 2 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 q0, nq0 output diffe rential output pair. lvpecl interface levels. 3, 4 q1, nq1 output diffe rential output pair. lvpecl interface levels. 5, 6 q2, nq2 output diffe rential output pair. lvpecl interface levels. 7, 8 q3, nq3 output diffe rential output pair. lvpecl interface levels. 9, 10 q4, nq4 output differential output pair. lvpecl interface levels. 11 v ee power negative supply pin. 12 clk_sel input pulldown clock select input. when high, sele cts clk1, nclk1 inputs. when low, selects clk0, nclk0 inputs. lvttl / lvcmos interface levels. 13 clk0 input pulldown non-inverting differential clock input. 14 nclk0 input pullup inverting differential clock input. 15 reserved reserve reserved pin. 16 clk1 input pulldown non-inverting differential clock input. 17 nclk1 input pullup inverting differential clock input. 18, 20 v cc power positive supply pins. 19 nclk_en input pulldown synchronizing clock enable. when low, clock outputs follow clock input. when high, q outputs are forced low, nq outputs are forced high. lvttl / lvcmos interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ics85314agi-11 revision f september 16, 2013 3 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer function tables table 3a. control input function table after nclk_en switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in figure 1. in the active mode, the state of the outputs are a function of the clk0, nclk0 and clk1, nclk1 inputs as described in table 3b. figure 1. nclk_en timing diagram table 3b. clock input function table inputs outputs nclk_en clk_sel selected source q[0:4] nq[0:4] 0 0 clk0, nclk0 enabled enabled 0 1 clk1, nclk1 enabled enabled 1 0 clk0, nclk0 disabled; low disabled; high 1 1 clk1, nclk1 disabled; low disabled; high inputs outputs input to output mode polarity clk0 or clk1 nclk0 or nclk1 q[0:4] nq[0:4] 0 1 low high differential-to-differential non-inverting 1 0 high low differential-to-differential non-inverting enabled disabled clk[0:1] nclk[0:1] nclk_en nq[0:4] q[0:4]
ics85314agi-11 revision f september 16, 2013 4 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v cc = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85 c table 4c. differential dc characteristics, v cc = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85 c note 1: v il should not be less than -0.3v note 2: common mode voltage is defined as v ih . item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuos current surge current 50ma 100ma package thermal impedance, ? ja 20 lead soic 20 lead tssop 46.2 ? c/w (0 lfpm) 73.2 ? c/w (0 lfpm) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v cc positive supply voltage 2.375 3.3 3.8 v i ee power supply current 80 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v cc + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current nclk_en, clk_sel v cc = v in = 3.8v 150 a i il input low current nclk_en, clk_sel v cc = 3.8v, v in = 0v -5 a symbol parameter test conditions minimum typical maximum units i ih input high current clk0, clk1 v cc = v in = 3.8v 150 a nclk0, nclk1 v cc = v in = 3.8v 5 a i il input low current clk0, clk1 v cc = 3.8v, v in = 0v -5 a nclk0, nclk1 v cc = 3.8v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode range; note 1, 2 0.5 v cc ? 0.85 v
ics85314agi-11 revision f september 16, 2013 5 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer table 4d. lvpecl dc characteristics, v cc = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85c note 1: outputs termination with 50 ? to v cc ? 2v. ac electrical characteristics table 5. ac characteristics, v cc = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85c note: all parameters measured at ? out unless otherwise noted. note: the cycle-to-cycle jitter on the input will equal the jitter on the output. the part does not add jitter. note: electrical parameters are guaranteed over the specified ambient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs on different devices o perating at the same supply voltage , same temperature, same frequ ency and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po ints. symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.4 v cc ? 0.9 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditions minimum typical maximum units f out output frequency 700 mhz tp lh propagation delay, low to high; note 1 ? ? 700mhz 1.0 1.4 1.8 ns t sk(o) output skew; note 2, 3 30 ps t jit buffer additive phase jitter, rms 156.25mhz, integration range: 12khz - 20mhz 0.170 0.200 ps 644.53125mhz, integration range: 12khz - 20mhz 0.060 0.200 ps t sk(pp) part-to-part skew; note 3, 4 350 ps t s setup time nclk_en to clk 50 ps t h hold time nclk_en to clk 50 ps t r / t f output rise/fall time 20% to 80% 200 700 ps odc output duty cycle skew ? ? 700mhz 45 55 %
ics85314agi-11 revision f september 16, 2013 6 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer 156.25mhz additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamen tal frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. the noise floor of the equipment can be higher or lower than the noise floor of the device. additive phase noise is dependent on both the noise floor of the input source and measurement equipment. measured using a rohde & schwarz sma100 as the input source. ssb phase noise dbc/hz offset from carrier frequency (hz)
ics85314agi-11 revision f september 16, 2013 7 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer 644.53125mhz additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamen tal frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. the noise floor of the equipment can be higher or lower than the noise floor of the device. additive phase noise is dependent on both the noise floor of the input sour ce and measurement equipment. measured using a rohde & schwar z sma100 as the input source. ssb phase noise dbc/hz offset from carrier frequency (hz)
ics85314agi-11 revision f september 16, 2013 8 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer parameter measureme nt information lvpecl output load test circuit output skew propagation delay differential input level part-to-part skew rms phase jitter scope qx nqx v ee v cc 2v -1.8v to -0.375v nqxnqx nqy nqy t pd nq[0:4] q[0:4] nclk[0:1] clk[0:1] v cmr cross points v pp v cc v ee nclk[0:1] clk[0:1] t sk(pp) part 1 part 2 nqx nqx nqy nqy
ics85314agi-11 revision f september 16, 2013 9 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer parameter measurement in formation, continued setup & hold time output duty cycle output rise/fall time t hold t set-up nclk_en nclk[0:1] clk[0:1] nq[0:4] q[0:4] nq[0:4] q[0:4]
ics85314agi-11 revision f september 16, 2013 10 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer application information wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that th e sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, match ed termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 2. recommended schematic for wiring a diff erential input to accept single-ended levels recommendations for unused input and output pins inputs: clk/nclk inputs for applications not requiring the us e of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. control pins all control pins have internal pulldown resistors; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs can be le ft floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
ics85314agi-11 revision f september 16, 2013 11 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer 3.3v differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 3a, the input termination applies for idt lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. clk/nclk input driven by an idt lvhstl driver figure 3c. clk/nclk input driven by a 3.3v lvpecl driver figure 3e. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver figure 3f. clk/nclk input driven by a 2.5v sstl driver r150 r250 1.8v zo = 50 zo = 50 clknclk 3.3v lvhstlidt lvhstl driver differentialinput 3 . 3v c l k n c l k 3 . 3v 3 . 3v lvpe cl diff e r e nti a l in p u t h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t clknclk differentialinput lvpecl 3.3v zo = 50 zo = 50 3.3v r150 r250 r250 3.3v r1100 lvds clknclk 3.3v receiver zo = 50 zo = 50 clknclk differentialinput sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1120 r2120 r3120 r4120
ics85314agi-11 revision f september 16, 2013 12 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer 2.5v differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver co mponent to confirm the driver termination requirements. for example in figure 3a, the input termination applies for idt lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. clk/nclk input driven by an idt lvhstl driver figure 3c. clk/nclk input driven by a 2.5v lvpecl driver figure 3e. clk/nclk input driven by a 2.5v hcsl driver figure 3b. clk/nclk input driven by a 2.5v lvpecl driver figure 3d. clk/nclk input driven by a 2.5v lvds driver figure 3f. clk/nclk input dri ven by a 2.5v sstl driver r1 50 ? r2 50 ? 1. 8v zo = 50 ? zo = 50 ? c l k nc l k 2 . 5v l vh s t l i dt o pen emitte r l vh s tl driv er d i ffe r e nti a l i nput r3 250 ? r4 250 ? r1 6 2. 5 ? r2 6 2. 5 ? 2 . 5v zo = 50 ? zo = 50 ? c l k nc l k 2 . 5v 2 . 5v l vpe cl differential i nput hc s l * r 333 * r4 33 clknclk 2.5v 2.5v zo = 50 zo = 50 differenti a l inp u t r150 r250 * option a l ? r 3 a nd r4 c a n b e 0 c l k nc l k d i ffe r e nti a l i nput l vpe cl 2 . 5v zo = 50 ? zo = 50 ? 2 . 5v r1 50 ? r2 50 ? r3 1 8 ? 2 . 5v r1 1 00 ? l vd s c l k nc l k 2 . 5v differential i nput zo = 50 ? zo = 50 ? clknclk differential input sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1120 r2120 r3120 r4120
ics85314agi-11 revision f september 16, 2013 13 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are low impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 5a. 3.3v lvpecl output termination figure 5b. 3.3v lvpecl output termination r184 ? r284 ? 3.3v r3125 ? r4125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v +_
ics85314agi-11 revision f september 16, 2013 14 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer termination for 2.5v lvpecl outputs figure 6a and figure 6b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 6b can be eliminated and the termination is shown in figure 6c. figure 6a. 2.5v lvpecl driver termination example figure 6c. 2.5v lvpecl driver termination example figure 6b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1250 r3250 r262.5 r462.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r150 r250 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r150 r250 r318 + ?
ics85314agi-11 revision f september 16, 2013 15 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer power considerations this section provides information on power dissipati on and junction temperature for the ics85314i-11. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics85314i-11 is the sum of the core power plus the power dissipated due to loading. the following is the power dissipation for v cc = 3.8v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated due to loading. ? power (core) max = v cc_max * i ee_max = 3.8v * 80ma = 304mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 5 * 30mw = 150mw total power_ max (3.6v, with all outputs switching) = 304mw + 150mw = 454mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliabil ity of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming a moderate air flow or 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6c/w per table 6b below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.454w * 66.6c/w = 115c. th is is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6a. thermal resistance ? ja for 20 lead soic, forced convection note: most modern pcb design use multi-layered boards. the data in the second row pertains to most designs. table 6b. thermal resistance ? ja for 20 lead tssop, forced convection note: most modern pcb design use multi-layered boards. the data in the second row pertains to most designs. ? ja by velocity linear feet per minute 0 200 500 single-layer pcb, jedec standard test boards 83.2c/w 65.7c/w 57.5c/w multi-layer pcb, jedec standard te st boards 46.2c/w 39.7c/w 36.8c/w ? ja by velocity linear feet per minute 02 0 05 0 0 single-layer pcb, jedec standard te st boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w
ics85314agi-11 revision f september 16, 2013 16 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pairs. lvpecl output driver circuit and termination are shown in figure 7. figure 7. lvpecl driver circuit and termination t o calculate power dissipation due to loading, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max ? v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l] * (v cc_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cc v cc - 2v q1 rl 50
ics85314agi-11 revision f september 16, 2013 17 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer reliability information table 7a. ? ja vs. air flow table for a 20 lead soic, forced convection note: most modern pcb design use multi-layered boards. the data in the second row pertains to most designs. table 7b. ? ja vs. air flow table for a 20 lead tssop, forced convection note: most modern pcb design use multi-layered boards. the data in the second row pertains to most designs. transistor count the transistor count for ics85314i-11 is: 674 ? ja by velocity linear feet per minute 02 0 05 0 0 single-layer pcb, jedec standard te st boards 83.2c/w 65.7c/w 57.5c/w multi-layer pcb, jedec standard test boards 46.2c/w 39.7c/w 36.8c/w ? ja by velocity linear feet per minute 0 200 500 single-layer pcb, jedec standard te st boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard te st boards 73.2c/w 66.6c/w 63.5c/w
ics85314agi-11 revision f september 16, 2013 18 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer package outlines an d package dimensions package outline - g suffix for 20 lead tssop table 8a. package dimensions reference document: jede c publication 95, mo-153 package outline - m suffix for 20 lead soic table 8b. package dimensions for 20 lead soic reference document: jedec pu blication 95, ms-013, ms-119 all dimensions in millimeters symbol minimum maximum n 20 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10 300 millimeters all dimensions in millimeters symbol minimum maximum n 20 a 2.65 a1 0.10 a2 2.05 2.55 b 0.33 0.51 c 0.18 0.32 d 12.60 13.00 e 7.40 7.60 e 1.27 basic h 10.00 10.65 h 0.25 0.75 l 0.40 1.27 ? 0 7
ics85314agi-11 revision f september 16, 2013 19 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer ordering information table 9. ordering information part/order number marking package shipping packaging temperature 85314agi-11lf ics5314ai11l ?lead-free? 20 lead tssop tube -40 ? c to 85 ? c 85314AGI-11LFT ics5314ai11l ?lead-free? 20 lead tssop tape & reel -40 ? c to 85 ? c 85314ami-11lf ics85314ami-11lf ?lead-free? 20 lead soic tube -40 ? c to 85 ? c 85314ami-11lft ics85314ami-11lf ?lead-free? 20 lead soic tape & reel -40 ? c to 85 ? c
ics85314agi-11 revision f september 16, 2013 20 ?2013 integrated device technology, inc. ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer revision history sheet rev table page description of change date a t1t2 22 4 7 8 pin description table - pin 14 & 17, nclkx, deleted partial description and added pullup in the ?type? column. pin characteristics table - c in changed 4pf max. to 4pf typical. amr - corrected output rating. added wiring the differential input to accept single ended levels section. added differential clock input interface section. 6/11/03 b t5 15 6 8 9 added phase noise bullet in features section. ac characteristics table - added rms phase jitter. added phase jitter plot. updated termination for 3.3v lvpecl output diagrams. added termination for 2.5v lvpecl output section. 8/11/04 bt 1 t9 12 16 features section - added lead-free bullet. pin description table - corrected clk_sel description. ordering information table - added ""lead-free"" part number for tssop package. 3/22/05 c t5 15 features section - changed part-to-part skew from 2 50ps max. to 350ps max. ac characteristics table - changed part-to- part skew from 250ps max. to 350ps max. 5/24/05 d t4d 5 8 lvpecl dc characteristics table - changed v oh max from v cc - 1.0v to v cc - 0.9v. application information section - added recommendations for unused input and output pins. 9/23/05 e t4c t5t9 45 9 17 differential dc characteristi cs table - corrected typo in i ih row, nclkx to 5ua from 150ua. added thermal note to ac characteristics table. updated ?wiring the differential input to accept single-ended levels? section. ordering information table - added lf marking for soic package. converted datasheet format. 4/16/10 e t9 17 ordering information table - corrected package in the package column. 5/4/10 f t5t9 15 6-7 8 1012 19 features section - updated packaging bullet. deleted rms phase noise bullet ac characteristics table - removed rms phase noise specification, and added buffer additive phase jitter specifications. removed rms phase noise plot, and replac ed with additive phase jitter plots. parameter measurement information - corrected phase noise diagram. updated wiring the differential inputs to accept single-ended levels application note. added 2.5v differential clock input interface application note. ordering information table - deleted leaded parts, deleted tape and reel count. 9/16/13
ics85314i-11 data sheet low skew, 1-to-5 differe ntial-to-2.5v, 3.3v lvpecl fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idts sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idts products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idts products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support sales netcom@idt.com +480-763-2056 weve got your timing solution

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